Fully depleted silicon-on-insulator (FDSOI) is a planar process technology that enables control of the behavior of transistors by polarizing the substrate underneath the device. This results in advantages of a reduced silicon geometries while simplifying the manufacturing process. Providing a high density solution to FDSOI such as coupling with split gate non-volatile memory (NVM) devices enables more efficient, reliable and re-programmable system at a low cost.
However, conventional split gate NVM devices utilizing FDSOI platform suffer several limitations, such as scalability issues or program disturbance. Further, there is also a desire to form split gate memory devices which can be integrated together with other types of devices to form embedded memory in a cost effective manner. As such, it is desirable to provide a split gate NVM cell with improved scalability, increased program/erase speed, minimized program disturbance and with improved endurance and a low cost methodology which can integrate logic and memory devices on the same chip.